The field of this invention relates to semiconductor memory devices and particularly to semiconductor memory cells comprising a combination of bipolar junction transistor technology and CMOS (complimentary metal oxide semiconductor) technology. More particularly, this invention relates to a Bi-CMOS (bipolar and CMOS) semiconductor memory cell for reading, writing and storing binary data.
Prior art Bi-CMOS semiconductor memory cells are often used where high speed in retrieving information from the memory cells is important. The high speed of these devices is significantly contributed to by the use of the bipolar transistors in conjunction with the MOS (metal oxide semiconductor) field effect transistors.
These Bi-CMOS semiconductor memory cells are typically faster (e.g., data may be retrieved more quickly) than semiconductor memory cells which utilize solely MOS or CMOS technology. An example of a prior art CMOS memory cell is shown in FIG. 2b (as memory cell 21) of U.S. Pat. No. 4,785,427. It can be seen from memory cell 21 in FIG. 2b of that patent that no bipolar devices are used to construct the memory cell 21. Consequently, these memory cells, constructed from field effect devices only, do not have the high speed bipolar inputs and outputs; moreover, these MOS and CMOS semiconductor memory cells do not have the stability over various temperatures and voltages of memory cells which utilize high speed bipolar inputs and outputs which have address accessing time that is relatively independent of voltage and temperature fluctuations. Accordingly, attempts have been made in the prior art to construct semiconductor memory cells which combine MOS field effect devices with bipolar devices; moreover, attempts have been made to combine CMOS configurations of MOS field effect devices with bipolar transistors in order to achieve faster reading and writing times.
An example of a prior art Bi-CMOS semiconductor memory cell is shown in FIG. 1. FIG. 1 shows a Bi-CMOS semiconductor memory cell (which has a single ended read line and a single ended write line) having MOS devices 17, 18, 19, 20 and 21 and the npn bipolar transistor 22. The p-channel MOS field effect devices 18 and 19 and the n-channel field effect devices 20 and 21 are coupled in the conventional, (so called) cross coupled inverter configuration to yield a bistable circuit means which has complimentary outputs. That is, the outputs of the bistable circuit means formed by MOS devices 18, 19, 20 and 21 have outputs which are complimentary (one output is the binary logical inverse of the other). MOS field effect device 17 couples the bistable circuit means to a write bit line 12 through the source/drain current path of device 17. The gate of device 17 is coupled to the write word line 11 which is taken high during writing to permit the data provided on the write bit line 12 to be read into the bistable circuit means during writing. The read word line 10 is coupled to the sources of p-channel devices 18 and 19 and the sources of n-channel devices 20 and 21 are coupled to V.sub.ee 15 which is a supply voltage, typically -5.2V. The bipolar transistor 22 includes a base and a collector and an emitter. As shown in FIG. 1, the base of bipolar transistor 22 is coupled to one of the complimentary outputs of the bistable circuit means formed by devices 18, 19, 20 and 21. The collector of bipolar transistor 22 is coupled to a supply voltage V.sub.cc 16 which is typically a power supply voltage (e.g., reference voltage), such as ground. It will be appreciated by those in the art that the semiconductor memory cell in FIG. 1 will typically utilize ECL (emitter coupled logic) logic levels so that V.sub.cc will typically be 0 volts and that V.sub.ee will be -5.2V. The emitter of bipolar transistor 22 is coupled to the read bit line 13 which is coupled to sense amplifier 23.
The Bi-CMOS ECL semiconductor memory cell shown in FIG. 1 is a static random access, read, write memory cell which has fast reading and writing times to permit high speed retrieval and writing of data. It will be appreciated that standard and well known peripheral circuitry used to select a particular cell in an array containing these cells will be utilized to activate the write word line and the read word line during writing and reading respectively. Moreover, it will be appreciated by those in the art that conventional, well known peripheral circuitry will be coupled to the write bit line 12 to provide input to the cell to write data into the cell during writing of the memory cell shown in FIG. 1. The Bi-CMOS ECL semiconductor memory cell shown in FIG. 1 will effect the status of the read bit line 13 and hence the output of a conventional sense amp 23 through the high speed bipolar transistor 22. Hence, the Bi-CMOS semiconductor cell shown in FIG. 1 will have improved speed as compared to semiconductor memory cells utilizing solely MOS field effect devices. However, the semiconductor memory cell in FIG. 1 has numerous disadvantages. For example, the reliability over time of the memory cell decreases because during normal operation the emitter base junction of the bipolar transistor 22 can become reversed biased by approximately 4 volts which causes hot electron trapping in the oxide around the junction between the emitter and the base of the transistor. This consequently decreases the beta of the transistor and long term reliability of the memory cell. The reverse biasing of transistor 22 occurs when the base of transistor 22 is pulled low with respect to the emitter of transistor 22, thereby reverse biasing the base/emitter junction of transistor 22. Moreover, the p-channel field effect devices 18 and 19 cannot be optimized for both read and write operations separately from the design considerations involved in driving the base of the bipolar transistor 22.
It is an object of the invention to provide a static, random access, read, write Bi-CMOS memory cell using ECL logic that has fast read and write time and fast recovery while also providing high reliability and high immunity against alpha particle induced soft errors (e.g., corruption of data). Moreover, it is an object of the invention that the semiconductor memory cell utilize the low power advantages of CMOS circuitry while at the same time providing high speed reading and writing with high reliability. Moreover, it is an object of the invention to provide a Bi-CMOS semiconductor memory cell wherein the complimentary output from the bistable CMOS flip-flop circuit means does not have to drive directly the base of the bipolar transistor drivers which drive the read bit lines.